Electronic devices utilizing semiconductor chips are mounted on substrates that physically support the chips and electrically transmit signals between the chips and other elements of the circuit. This configuration is referred to as a package. Often, more than one chip or electronic assembly is included in a single package. Such multi-chip packages 1, as shown in FIG. 1, contain multiple semiconductor components (elements 2, 3, 4) in close proximity, each with independent heat dissipations. Each component also heats the adjacent components. The relative heat dissipation of each component is a function of the component's operation. Thus, it is important to accurately test the thermal resistance characterizations of multiple-chip packages having multiple heat sources in a test-mode. The junctions between the components in a multiple-chip package offer many useful properties, such as the capability to measure temperatures deep inside solid-state devices without direct mechanical or optical contact.
Existing test systems currently available only work well with single-chip packages. Such systems, as described in Dr. John W. Sofia's article “ELECTRICAL TEMPERATURE MEASRUEMENT USING SEMICONDUCTORS” (ElectronicsCooling, v. 3, no. 1, January 1997) herein incorporated by reference, measure junction-temperatures in single-chip packages by measuring a temperature-sensitive parameter (commonly known as “TSP”) of a device. TSPs can include diode forward voltage (i.e., for diodes, ICs, bipolar transistors, MOSFETs, etc.), saturation voltage (i.e, for bipolar transistors), and gate turn-on threshold (i.e., for bipolar transistors). Once an appropriate TSP is chosen, the relationship between the electrical entity and temperature is determined through device calibration by any method known in the art. Device calibration involves forcing the semiconductor to a known temperature and then measuring the TSP voltage associated with that temperature. This generates a linear calibration equation. Once this formula is determined, measurements of thermal impedances and resistances associated with single-device packages can be performed by measuring the junction temperature response to a measured heat dissipation from within the device, as shown in FIG. 2.
For multiple-chip packages, current test systems can only power one device at a time. Thus, direct measurement of junction temperatures for multiple-chip packages is not currently available.
Current test systems employ a linear superposition approach to obtain the junction temperatures for multiple-chip packages in a test-mode based on individual device test results. This method can be best understood in reference to FIGS. 3A-3C. In FIG. 3A, a theoretical device which contains two internal heat sources is insulated everywhere but at the points where a fixed temperature is imposed. When only a single heat source 1 is operating, the temperature at point T1 equals T11 and at point T2 equals T21. In FIG. 3B, when heat source 2 is operating and heat source 1 is not, the temperature at point T1 equals T12 and at point T2 equals T22. Using the method of linear superposition, the solution in FIG. 3C can be simply created by adding the temperature rises from each single source.
The method of superposition can be expressed as a matrix of thermal resistance formulations for multiple heat source thermal problems generated using the single-chip package measurement technique. In the theoretical example shown in FIGS. 3A-3C, the device is insulated everywhere but where a fixed temperature is imposed. Assuming that these uninsulated points are exposed to an infinite heat sink of temperature T0, the reference temperature is the infinite heat sink temperature, i.e., Tref=T0. Superimposing FIGS. 3A and 3B, the temperature rise of point 1 equals the temperature rise of point 1 with only the heat source at point 1 operating plus the temperature rise of point 1 with only the heat source 2 operating, thus:T1=(T11−T0)+(T12−T0)+T0T2=(T21−T0)+(T22−T0)+T0where the single-source temperatures are defined:                T11=temperature of point 1 with heating from point 1        T22=temperature of point 2 with heating from point 2        T12=temperature of point 1 with heating from point 2        T21=temperature of point 2 with heating from point 1and the superimposed temperatures are:        T1=temperature of point 1 due to heat from both point 1 and point 2;        T2=temperature of point 2 due to heat from both point 1 and point 2.The superposition solution can be expressed in terms of thermal resistances:       R    11    =                    T        11            -              T        0                    Q      1      Where all thermal resistences are from the heat source “junctions” to the reference temperature Tref or T0. This yields a 2 by 2 matrix, |R|:                                                               R              11                                                          R              12                                                                          R              21                                                          R              22                                                  ⁢                   ⁢                                                            Q              1                                                                          Q              2                                                  *                                                            T1              -              T0                                                                                          T2                -                T0                            ⁢                                                                                                   thus:                              R                    *                      Q                      =                        Δ        ⁢                                   ⁢        T                  The general thermal resistance description of a component having ‘N’ heat sources is an N-by-N matrix, |R|. The heat dissipation of each source is formed into a column matrix, |Q|. The differences between the source temperatures and the reference temperatures also form a column matrix |ΔT|, where with the elements of the array are equal to Ti−Tref for I=1 to N. With the thermal resistance matrix determined, the temperature of each source can be calculated from the matrix equation based on the principle of superposition.        
The known method of linear superposition fails to take into account the non-lienarity of thermal systems and the error between this test-mode method and actual results (i.e., in operating mode) can be as high as 20% in most cases. In addition, the power distribution ratio of each device in a multiple-chip package under test must be separately measured. Further, direct measurement of junction temperatures for multiple-chip packages requires the development of complicated hardware systems, which is quite costly.